1. Field of the Invention
The present invention relates to a structure and a manufacturing method of an image TFT array, and more particular, to a structure and a manufacturing method of an image TFT array of an X-ray image sensor.
2. Description of the Prior Art
Recently, electronic matrix arrays find considerable application in X-ray image sensors. Such X-ray image sensors generally include scanning lines and data lines transversely and longitudinally spaced apart and across at an angle to one another, thereby forming a plurality of crossover points. Associated with each crossover point is an element or a pixel to be selectively addressed. These elements in many instances are memory cells or pixels of an electronically adjustable memory array or X-ray image TFT array.
A manufacturing method of an X-ray image TFT array according to the prior art includes seven photolithographic and etching processes. At first, the seven processes are concisely described as follows.
The first photolithographic and etching process includes forming a first metal layer and performing a photolithographic and etching process to form a lower electrode and a common electrode;
The second photolithographic and etching process includes forming a first insulating layer (SiNx) and a second metal layer in sequence and performing a photolithographic and etching process to form a gate, a pad, and an upper electrode;
The third photolithographic and etching process includes forming a second insulating layer (SiNx or SiNx/SiOx/SiNx), an amorphous-silicon layer, and a doping layer such as an n+ amorphous-silicon layer in sequence, and performing a photolithographic and etching process to define a semiconductor island;
The fourth photolithographic and etching process includes performing a photolithographic and etching process, especially a photolithographic and wet etching process, to form through holes on a storage capacitor, common electrode, and pad;
The fifth photolithographic and etching process includes forming a third metal layer and performing a photolithographic, a third metal layer wet etching, and a channel etching process, especially a channel dry etching process, to define the third metal layer and the back channel regions of thin film transistors;
The sixth photolithographic and etching process includes forming a passivation layer and performing a photolithographic and etching process to form a through hole on the insulating layer for forming a storage capacitor; and
The seventh photolithographic and etching process includes performing a photolithographic and etching process to form pixel electrodes of thin film transistors and outer test patterns to complete the manufacturing method of an X-ray image TFT array according to the prior art.
Next, the above manufacturing method is interpreted with FIG. 1 to FIG. 6 as follows. FIG. 1 to FIG. 6 are schematic diagrams of a manufacturing method for a thin film transistor (TFT) array 10 for an X-ray image TFT array according to the prior art. As shown in FIG. 1, a substrate 12 is provided. The substrate 12 can be a transparent glass or quartz substrate. Then, a first metal layer (not shown in FIG. 1) is deposited on the substrate 12. A first photolithographic and etching process is performed to remove a portion of the first metal layer to form a lower electrode 16 and a common electrode 18.
As shown in FIG. 2, a first insulating layer 20 and a second metal layer (not shown in FIG. 2) are deposited on the substrate 12 in sequence. A second photolithographic and etching process is performed to remove a portion of the second metal layer to form a gate 24, an upper electrode 26, and a pad 28 on the first insulating layer 20. It is noted that the lower electrode 16, the first insulating layer 20, and the upper electrode 26 constitute a storage capacitor.
Please refer to FIG. 3. A second insulating layer 30, an amorphous-silicon layer 32, and a doping layer 34 are deposited on the substrate 12. A third photolithographic and etching process is performed to remove a portion of the amorphous-silicon layer 32 and the doping layer 34 to define a semiconductor island 36.
As shown in FIG. 4, a fourth photolithographic and etching process, especially a photolithographic and wet etching process, is performed to remove a portion of the second insulating layer 30 and the first insulating layer 20 to form a first through hole 38 on the storage capacitor, a second through hole 40 on the pad 28, and a third through hole 42 on the common electrode 18.
As shown in FIG. 5, a third metal layer 44 is formed on the substrate 12. A fifth photolithographic and etching process, especially a photolithographic and wet etching process, is performed to remove a portion of the third metal layer 44 and a etching process, especially a dry etching process, is performed to form a channel 46 to define the third metal layer 44.
As shown in FIG. 6, a passivation layer 48 is deposited. A sixth photolithographic and etching process is performed to remove a portion of the passivation layer 48 to form a fourth through hole 50 on the storage capacitor. Finally, a seventh photolithographic and etching process is performed to form outer test patterns (not shown in FIG. 6) to complete the manufacturing method of the X-ray image TFT array 10 according to the prior art.
There are as many as seven photolithographic and etching processes in the prior art. Due to the high number of photolithographic and etching processes, the particle issue produced in the transferring and etching process is more serious. Moreover, since the manufacturing process is complicated, the manufacturing time is longer and the quantity of output is influenced.
For simplifying the above-mentioned process of the manufacturing method of an X-ray image TFT array, U.S. Pat. No. 6,764,900 discloses a manufacturing method that applies a half-tone process in an image TFT array. Please refer to FIG. 7 and FIG. 8. FIG. 7 and FIG. 8 are schematic diagrams of a manufacturing method that applies a half-tone process in an image TFT array. As shown in FIG. 7, a second insulating layer 1110 is situated on a gate 1020 and a substrate 1000. The gate 1020 is composed of a first metal. Then, an amorphous-silicon layer 1120, a doping layer 1130, and a conductive layer 1140 are deposited on the second insulating layer 1110 in sequence. A half-tone process is performed to form a patterned photoresist layer 1150 on the conductive layer 1140.
As shown in FIG. 8, utilizing the patterned photoresist layer 1150 as a mask, several etching processes are performed to remove a portion of the conductive layer 1140, the doping layer 1130, and the amorphous-silicon layer 1120 to form a common electrode 1210 on a first semiconductor island 1220 and a source region 1230, a drain region 1240, and a data line 1250 on a second semiconductor island 1260. The source region 1230, the drain region 1240, and the data line 1250 on the second semiconductor island 1260 form a thin film transistor structure.
However, U.S. Pat. No. 6,764,900 discloses that a half-tone process is applied for forming a common electrode and a thin film transistor, and does not disclose that the half-tone process could be applied for forming a thin film transistor, a storage capacitor, a common electrode, and a pad simultaneously. Furthermore, a structure of the X-ray image TFT array according to U.S. Pat. No. 6,764,900 is different from the present invention.